1. Field of the Invention
This invention relates to a buffer circuit.
2. Description of the Prior Art
FIG. 5 shows the structure of a typical prior art buffer circuit. In the prior art buffer circuit shown in FIG. 5, an operational amplifier circuit 1 is connected at its output terminal to a load so as to drive the load, while, at the same time, its output is fed back to its inverting input terminal, and an input signal 2 is applied to its non-inverting input terminal.
It is known that, when a capacitive load 3 is connected to the output terminal of the prior art buffer circuit as shown in FIG. 5, great ringing tends to occur, with the result that the settling time is extended or, in some case, undesirable oscillation is given rise to. (This fact is described in, for example, a book entitled "Design of Operational Amplifier circuits, Second Series" pages 70 and 71, , written by Okamura and published by CQ publishing Company.) The above situation is shown in FIG. 6. It will be seen in FIG. 6 that, when the input signal level changes stepwise as shown by the one-dot chain curve, ringing occurs in the output waveform shown by the solid curve, with the result that the settling time is inevitably extended.
The ringing occurs in the prior art buffer circuit shown in FIG. 5 for the reason that the direct connection of the capacitive load to the feedback circuit system decreases the phase margin of the feedback circuit system. This problem is usually solved by increasing the phase compensation capacity of the operational amplifier. However, this increase in the phase compensation capacity of the operational amplifier increases the response time constant of the circuit system. In addition, when the load capacity is to be changed, it is necessary to correspondingly change the internal phase compensation capacity. Thus, it has been practically difficult to buffer a high speed pulse signal.